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August 2003 Advance Information
PulseC re AS80SSTVF16859
DDR 13-Bit to 26-Bit Registered Buffer
Features
* * * * Differential clock signals Meets SSTL_2 class II specifications on outputs Low voltage operation - VDD = 2.3 V to 2.7 V Available in 64-pin TSSOP and 56-pin VFQFN packages (MLF2)
Recommended Applications
* * * DDR memory modules: PC1600, PC2100, PC2700, AND PC3200 Provides complete DDR DIMM logic solution with PCV857 SSTL_2-compatible data registers
Block Diagram
CLK CLKB RESETB D1 VREF R CLK D1 Q1A Q1B
Pin Configurations
Q13A Q12A Q11A Q10A Q9A VDDQ GND Q8A Q7A Q6A Q5A Q4A Q3A Q2A GND Q1A Q13B 42 D10 VDDQ D9 Q12B D8 Q11B D7 RESETB Q10B Q9B GND Q8B CLKB Q7B CLK Q6B VDDQ VDD GND VREF VDDQ D6 Q5B D5 Q4B 29 D4 Q3B Q2B Q1B
To 12 other channels
Q7A 1 Q6A Q5A Q4A Q3A Q2A Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B 14
AS80SSTVF16859
56-Pin VFQFN (MLF2)
6.10 mm body, 0.50 mm pitch
1 64 2 63 3 62 61 4 5 60 59 6 58 7 57 8 56 9 55 10 54 11 53 12 13 52 51 14 15 50 49 16 48 17 47 18 46 19 20 45 44 21 43 22 42 23 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 64-Pin TSSOP
AS80SSTVF16859
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Q7B 15 Q6B VDDQ Q5B Q4B Q3B Q2B Q1B VDDQ D1 D2 VDD VDDQ D3 28
VDDQ GND D13 D12 VDD VDDQ GND D11 D10 D9 GND D8 D7 RESETB GND CLKB CLK VDDQ VDD VREF D6 GND D5 D4 D3 GND VDDQ VDD D2 D1 GND VDDQ
56 Q8A VDDQ Q9A Q10A Q11A Q12A Q13A VDDQ GND D13 D12 VDD VDDQ 43 D11
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AS80SSTVF16859
Truth Table1
Inputs RESETB L H H H CLK X or floating

Q outputs CLKB X or floating

D X or floating H L X
Q L H L Q 02
L or H
L or H
1 H = high signal level, L = low signal level, = transition low to high, = transition high to low, X = don't care. 2 Output level before the indicated steady state input conditions were established.
Description
The 13-bit to 26-bit PC16859 is a universal bus driver designed for 2.3 V to 2.7 V VDD operation and SSTL_2 I/O levels, except for the LVCMOS RESETB input. Data flow from D to Q is controlled by the differential clock (CLK/CLKB) and a control signal (RESETB). The positive edge of CLK is used to trigger the data flow, and CLKB is used to maintain sufficient noise margins, whereas RESETB, an LVCMOS asynchronous signal, is intended for use only at power-up. PC16859 supports low-power standby operation. A logic level low at RESETB assures that all internal registers and outputs (Q) are reset to the logic low state, and that all input receivers, data (D), and clock (CLK/CLKB) are switched off. Note that RESETB must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-up. To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held at a logic low level during power-up. In the DDR DIMM application, RESETB is specified to be completely asynchronous with respect to CLK and CLKB, therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state, the register will be cleared and the outputs will be driven to a logic low level quickly relative to the time to disable the differential input receivers. This ensures there are no glitches on the output. When coming out of low power standby state, however, the register will become active quickly relative to the time to enable the differential input receivers. When the data inputs are at a logic level low and the clock is stable during the low-tohigh transition of RESETB until the input receivers are fully enabled, the design ensures that the outputs will remain at a logic low level.
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Pin Configuration (64-Pin TSSOP)
Pin number 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 16, 17, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30, 31, 32 7, 15, 26, 34, 39, 43, 50, 54, 58, 63 6, 18, 27, 33, 38, 47, 59, 64 35, 36, 40, 41, 42, 44, 52, 53, 55, 56, 57, 61, 62 48 49 37, 46, 60 51 45 Pin name Q(13:1) GND VDDQ D(13:1) CLK CLKB VDD RESETB VREF Type Output PWR PWR Input Input Input PWR Input Input Data output Ground Output supply voltage, 2.5 V nominal Data input Positive master clock input Negative master clock input Core supply voltage, 2.5 V nominal Reset (active low) Input reference voltage, 1.25 V nominal Description
Pin Configuration (56-Pin MLF2)
Pin number 1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22, 50, 51, 52, 53, 54, 56 37, 48 9, 17, 23, 27, 34, 44, 49, 55 24, 25, 28, 29, 30, 31, 39, 40, 41, 42, 43, 46, 47 35 36 26, 33, 45 38 32 - Pin name Q(13:1) GND VDDQ D(13:1) CLK CLKB VDD RESETB VREF Center pad Type Output PWR PWR Input Input Input PWR Input Input PWR Data output Ground Output supply voltage, 2.5 V nominal Data input Positive master clock input Negative master clock input Core supply voltage, 2.5 V nominal Reset (active low) Input reference voltage, 1.25 V nominal Ground (VFQFN package only) Description
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Absolute Maximum Ratings
Storage temperature Supply voltage Input voltage Output
1
- 65 C to +150 C -0.5 to 3.6 V -0.5 to VDD + 0.5 -0.5 to VDD + 0.5 50 mA 50 mA 50 mA 100 mA 55 C/W
3
voltage1,2
Input clamp current Output clamp current Continuous output current VDD, VDDQ, or GND current/pin Package thermal impedance
1 The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2 This current will flow only when the output is in the high state level V0 > VDDQ. 3 The package thermal impedance is calculated in accordance with JESD 51.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only, and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Recommended Operating Conditions - DDRI / DDR333 (PC1600, PC2100, PC2700)
Guaranteed by design. Not 100% tested in production. Parameter VDD VDDQ VREF VTT VI VIH(DC) VIH(AC) VIL(DC) VIL(AC) VIH VIL VICR VID VIX IOH IOL TA
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Description Supply voltage I/O supply voltage Reference voltage Termination voltage Input voltage DC input high voltage AC input high voltage DC input low voltage AC input low voltage Input high voltage level Input low voltage level RESETB Data inputs
Min 2.3 2.3 1.15 VREF - 0.04 0 VREF + 0.15 VREF + 0.31
Typ 2.5 2.5 1.25 VREF
Max 2.7 2.7 1.35 VREF + 0.04 VDD
Units V V V V V V V
VREF - 0.15 VREF - 0.31 1.7 0.7 0.97 0.36 (VDDQ/2) - 0.2 (VDDQ/2) + 0.2 -20 20 0 70 1.53
V V V V V V V mA mA C
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Common mode input range CLK. CLKB Differential input voltage Cross-point voltage of differential clock pair High-level output current Low-level output current Operating free-air temperature
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AS80SSTVF16859
Recommended Operation Conditions - DDRI-400 (PC3200)
Guarenteed by design, not 100% tested in production. Parameter VDD VDDQ VREF VTT VI VIH(DC) VIH(AC) VIL(DC) VIL(AC) VIH VIL VICR VID VIX IOH IOL TA Supply Voltage I/O supply voltage Reference voltage Termination voltage Input voltage DC input high voltage AC input high voltage DC input low voltage AC input low voltage Input high voltage level Input low voltage level Common mode input range Differential input voltage Cross-point voltage of differential clock pair High-level output current Low-level output current Operating free-air temperature 0 RESETB CLK, CLKB 1.7 0.7 0.97 0.36 (VDDQ/2) - 0.2 (VDDQ/2) + 0.2 -16 16 70 1.53 Data Inputs Description Min 2.5 2.5 1.25 VREF - 0.04 0 VREF + 0.15 VREF + 0.31 VREF - 0.15 VREF - 0.31 Typ 2.6 2.6 1.3 VREF Max 2.7 2.7 1.35 VREF + 0.04 VDDQ Units V V V V V V V V V V V V V V mA mA C
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DC Electrical Characteristics - DDRI / DDR333 (PC1600, PC2100, PC2700)
TA = 0 C to 70 C, VDD = 2.5 0.2 V, and VDDQ = 2.5 0.2 V (unless otherwise stated) Guaranteed by design. Not 100% tested in production.. Symbol VIK VOH Parameters Test conditions II = -18 mA IOH = -100 A IOH = -16 mA VOL II IDD All inputs Standby (static) Operating (static) Dynamic operating (clock only) IOL = 100 A IOL = 16 mA VI = VDD or GND RESETB = GND VI = VIH(AC) or VIL(AC), RESETB = VDD RESETB = VDD, VI = VIH(AC) or VIL(AC), CLK and CLKB switching 50% duty cycle RESETB = VDD, VI = VIH(AC) or VIL(AC), CLK and CLKB = switching 50% duty cycle One data input switching at half clock frequency, 50% duty cycle IOH = -20 mA IOL = 20 mA IO = 20 mA, TA = 25 C VI = VREF 310 mV, VICR = 1.25 V, VI(PP) = 360 mV VI = VDD or GND 2.3 V to 2.7 V 2.3 V to 2.7 V 2.5 V 2.5 V 2.5 V 2.5V 2.5 2.5 2.5 7 7 20 20 4 3.5 3.5 3.5 VDD 2.3 V 2.3 V to 2.7 V 2.3 V 2.3 V to 2.7 V 2.3 V 2.7 V 2.7 V 2.7 V VDD 0.2 1.95 0.2 0.35 5 0.01 25 Min Typ Max -1.2 Units V V V V V A A mA A/ clock MHz / clock MHz/ data input pF pF pF
2.7 V IO = 0
30
IDDD Dynamic operating (per each data input)
2.7 V
10
rOH rOL rO(D)
Output high Output low |rOH - rOL| each separate bit Data inputs
Ci
CLK and CLKB RESETB
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DC Electrical Characteristics - DDRI-400 (PC3200)
TA = 0 C to 70 C, VDD = 2.6 0.1 V, and VDDQ = 2.6 0.1 V (unless otherwise stated) Guaranteed by design. Not 100% tested in production.. Symbol VIK VOH Parameters Test conditions II = -18 mA IOH = -100 A IOH = -8 mA VOL II IDD All inputs Standby (static) Operating (static) Dynamic operating (clock only) IOL = 100 A IOL = 8 mA VI = VDD or GND RESETB = GND VI = VIH(AC) or VIL(AC), RESETB = VDD RESETB = VDD, VI = VIH(AC) or VIL(AC), CLK and CLKB switching 50% duty cycle RESETB = VDD, VI = VIH(AC) or VIL(AC), CLK and CLKB = switching 50% duty cycle One data input switching at half clock frequency, 50% duty cycle IOH = -16 mA IOL = 16 mA IO = 20 mA, TA = 25 C VI = VREF 310 mV, VICR = 1.25 V, VI(PP) = 360 mV VI = VDD or GND 2.5 V to 2.7 V 2.5 V to 2.7 V 2.6 V 2.6 V 2.6 V 2.6V 2.5 2.5 2.5 7 7 20 20 4 3.5 3.5 3.5 VDD 2.5 V 2.5 V to 2.7 V 2.5 V 2.5 V to 2.7 V 2.5 V 2.7 V 2.7 V 2.7 V VDD 0.2 1.95 0.2 0.35 5 0.01 25 Min Typ Max -1.2 Units V V V V V A A mA A/ clock MHz / clock MHz/ data input pF pF pF
2.7 V IO = 0
30
IDDD Dynamic operating (per each data input)
2.7 V
10
rOH rOL rO(D)
Output high Output low |rOH - rOL| each separate bit Data inputs
Ci
CLK and CLKB RESETB
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Timing Requirements
(Over recommended operating free-air temperature range, unless otherwise noted.) Guaranteed by design. Not 100% tested in production * This parameter is not necessarily production tested..
VDDQ = 2.5V0.2V VDDQ = 2.6V0.1V
Units MHz ns ns ns ns ns ns ns
Symbol fCLOCK tW tACT*
tINACT*
Parameters Clock frequency Pulse duration, CK, CKLB high or low Differential inputs active time Differential inputs inactive Setup time, slow slew rate Hold time, fast slew Hold time, slow slew Setup time, fast slew rate3,5
4,5 1
Min 2.5
Max 200
Min 2.5
Max 270 22 22
22 22 Data before CLK, CLKB Data after CLK, CLKB 0.75 0.9 0.75 0.9 0.4 0.6 0.4 0.6
time2
tS th
rate3,5 rate4,5
1 Data inputs must be low a minimum time of tACT max, after RESETB is taken high 2 Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max, after RESETB is taken low 3 For data signal input slew rate > 1 V/ns 4 For data signal input slew rte > 0.5 V/ns and < 1 V/ns 5 CLK, CLKB signals iput slew rates are > 1 V/ns
Switching Characteristics - DDRI / DDR333 (PC1600, PC2100, PC2700)
(Over recommended operating free-air temperature range unless otherwise noted.) VDD = 2.5 V 0.2 V Symbol fmax tPD tphl CLK, CLKB (TSSOP) CLK, CLKB (VFQFN[MLF2]) RESETB Q Q Q From (input) To (output) Min 200 1.1 1.1 - - Typ - Max - 2.8 2.8 5.0 Units MHz ns ns ns
Switching Characteristics - DDRI-400 (PC3200)
(Over recommended operating free-air temperature range unless otherwise noted.) VDD = 2.6 V 0.1 V Symbol fmax tPD tPDSS tphl CLK, CLKB (VFQFN[MLF2]) Simultaneous switching RESETB Q Q Q From (input) To (output) Min 210 1.1 2.2 2.48 3.5 Typ Max Units MHz ns ns ns
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Parameter Measurement Information (VDD = 2.5 V 0.2 V)
VTT RL = 50 From output under test Test point CL = 30 pF1 Load circuit
1
CL includes probe and jig capacitance.
Voltage and Current Waveforms
In the following waveforms, note that all input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Zo = 50 , input slew rate = 1 V/ns 20% (unless otherwise specified). The outputs are measured one at a time with one transition per measurement. VTT = VREF = VDDQ/2. VIH = VREF + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. VIL = VREF - 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. tPLH and tPHL are the same as tpd. Input active and inactive times
LVCMOS RESETB VDD 0V tinact 10%
1
Input
IDD
1
VDD/2
VDD/2 tact 90%
IDDH IDDL
IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Pulse duration tw Input VREF VREF VIH VIL
Setup and hold times VI(pp) Timing input ts Input VREF VICR th VREF VIH VIL
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Propagation delay times
VI(pp) Timing input VICR tPLH VTT VICR tPHL VTT VOH VOL
Output
LVCMOS RESETB Input VDD/2 tPHL Output VTT
VIH VIL
VOH VOL
LOW-TO-HIGH SLEW RATE MEASUREMENT
dt_r dV_r VOH 80% Output 20% VOL
HIGH-TO-LOW SLEW-RATE MEASUREMENT
VOH 80% Output 20% dV_f dt_f VOL
Output slew rates over recommended operating free-air temperature range (unless otherwise noted) VCC= 2.5 V + 0.2V * Parameter dV/dt_r dV/dt_f dV/dt_
VCC = 2.6 V + 0.1 V * Min 1 1 Max 4 4 1 Unit V/ns V/ns V/ns
From 20% 80%
To 80% 20%
Min 1 1
Max 4 4 1
20% or 80% 80% or 20%
*For this test condition, VDDQ is always equal to VDD **Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
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Package Dimensions (64- Pin TSSOP)
Millimeters N c L Symbol A A1 E1 Index area 12 D A2 e b A1 A
Seating plane
Inches Min - 0.002 0.32 0,007 0.0035 Max 0.047 0.006 0.041 0.011 0.008
Min - 0.05 0.80 0.17 0.09
Max 1.20 0.15 1.05 0.27 0.20
E
A2 b c D E E1 e L N aaa Variations: aaa C
See variations below 8.10 basic 6.00 0.45 0 - 6.20 0.75 8 0.10 0.50 basic 0.319 basic 0.236 0.018 0 - 0.244 0.030 8 0.004 0.020 basic
See variations below
6.10 mm (240 mil) body, 0.50 mm (0.020 mil) pitch TSSOP
D (mm) N 64 Min 16.90 Max 17.10
D (inch) Min 0.665 Max 0.673
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Package Dimensions (56-Pin MLF2)
D D/2 D1 D1/2 0.18 Dia.
0.25 C A A 0.25 C B A2 A1 A3
Common dimensions Symbol A A1 A2 A3 0.00 Min Typ 0.85 0.01 0.65 0.20 BSC 8.00 BSC 7.75 BSC 8.00 BSC 7.75 BSC 12 0.24 0.13 0.42 0.17 0.50 BSC 56 14 14 0.30 0.18 0.00 4.35 5.05 0.40 0.23 0.20 4.50 5.20 0.50 0.30 0.45 4.65 5.35 0.60 0.23 Max 1.00 0.05 0.80
E1
E
D D1 E E1
Seating plane
E1/2 E/2
0.20 C B 0.20 C A Top view
P R
Side view
Pitch variation D e N
4x P D2
0.25 C A B D2/2 Pin ID
Nd Ne L b
0.35
4x P
Q D2 E2
E2
(Ne - 1) X e
E2/2 L e (Nd - 1) X e
b
Bottom view
A1 Terminal tip For odd terminal/side For even terminal/side Cross section
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Ordering Information
Ordering Number AS80SSTVF16859-64TT AS80SSTVF16859-64TR AS80SSTVF16859-56KT AS80SSTVF16859-56KR
Marking AS80SSTVF16859T AS80SSTVF16859T AS80SSTVF16859K AS80SSTVF16859K
Package 64-Pin TSSOP, Tube 64-Pin TSSOP, Tape & Reel 56-pin MLF2, Tube 56-pin MLF2, Tape & Reel
Qty per Reel Temperature 0C to 70C 2500 0C to 70C 0C to 70C 2500 0C to 70C
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(c) Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

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